1. Field of the Invention
The present invention relates to a method and an apparatus for supporting verification in large-scale integration (LSI) design, and a computer product.
2. Description of the Related Art
In LSI design, improvement of work efficiency by shortening a design period has conventionally been demanded. However, in the LSI design, a verification process, which is rather time consuming, to verify whether an LSI properly operates is essential. Especially for an LSI that is required to be large-scale, to have high performance, to be high-speed, and to be low-power consuming, the verification process is important to maintain high quality.
In the verification process currently carried out, a verification item list in a free format is used. The verification item list is formed in a table, and verification items that are extracted from a specification of an LSI by a third party, such as an outsider, an outside segment, and an outside company, are listed up in the table. A format of the verification item list is not standardized, and is different among third parties.
Moreover, a technology for objectively evaluating necessity and sufficiency of the verification items in the verification item list has not been established. Therefore, there is no numerical ground that the verification items are necessary and sufficient. With such reason, currently, the verification process is carried out while a person that is engaged in the verification process (a designer of the LSI) or other members review whether all necessary verification items are picked up from the specification of the LSI.
On the other hand, an apparatus for supporting the verification process is proposed. In the apparatus, the verification list is automatically obtained by using a computer-readable electronic specification that is written in an object oriented unified modeling language (UML). Such a technology is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-185592. The apparatus includes a functional-structure-information input unit, a condition input unit, a verification-item-function creating unit, and a verification-item extracting unit. The functional-structure-information input unit inputs functional structure information that indicates functions of a verification target device to be verified whether the verification target device operates properly. The condition input unit inputs conditions relating to input/output sequences to be provided to the verification target device. The verification-item-function creating unit creates a verification item function that completely satisfies the conditions based on the functional structure information. The verification-item extracting unit extracts a combination of elements that form the functional structure information as a verification item, based on the verification item function.
In the above conventional verification process that includes a review process, a result of review for evaluating a quality of the verification items is dependent on experience and ability of the members involved in the review. In other words, in the conventional verification process, the verification items are extracted without reference.
Therefore, in some cases, necessary verification items are missed to be extracted, or unnecessary verification items are undesirably extracted. Thus, the result of the review varies, and verification coverage obtained as a result of the review decreases. In addition, this reduces a yield in actual manufacturing of the LSI.
Moreover, because the review requires 3 to 10 people or more to be involved as review members, schedule arrangement itself can be a trouble for a coordinator, taking time and labor. In addition, if the schedule arrangement does not proceed smoothly, a reviewing period becomes long. Thus, a total time required for the LSI design increases. Furthermore, the review usually requires about two hours to half a day. This not only makes the verification period long, but also causes a delay in other processes in the LSI design because of binding hours constraints for the members.
In the conventional technology disclosed in the patent literature, it is possible to automatically obtain an updated verification item list created based on an updated electronic specification, even if the electronic specification is updated for an additional function of the LSI. However, to identify new verification items added in the updated verification item list, it is necessary to manually compare the verification item list before update of the electronic specification and the updated item list. Therefore, the verification process requires a great deal of time and labor. This makes the design period long, and increases manufacturing cost.